1. Field of the Invention
This invention relates generally to electronic design automation (EDA) systems used for designing integrated circuits. The invention is more specifically related to a method and apparatus for optimizing a circuit design having multi-cycle paths therein.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. Chip designers generally employ hierarchial design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip's functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a "behavior description"). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually are logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
It is useful to distinguish between those components of an integrated circuit design called cells, provided by a silicon chip vendor as primitive cells (i.e., leaf candidates), and the user-defined hierarchy blocks built upon them. One way is to speak of a "cell library" vs. a "design library" as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design. Initial cell library contents are usually provided by the chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term "NAND" for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND., When a 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip.
A single name is sufficient when dealing only in the context of a single user function. The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy may be a single block that defines the entire design, and the bottom layer of the hierarchy may consist of leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library. The resulting design is often called a detailed (or gate-level) description of the logic design.
The generation of the detailed description is often accomplished by logic design synthesis software for HDL entry. The logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors may be detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description.
The output of the design capture and synthesis tools is typically a logic design database which completely specifies the logical and functional relationships among the components of the design. Once the design has been converted into this form, it may be optimized by sending the logic design database to a logic optimizer tool typically implemented in software.
In many logic optimizer tools, the optimization process may include a characterization step and an optimization step. During the characterization step, various optimization parameters are assigned to selected portions of the design. For example, for those portions of the design that are to be optimized for timing, the characterization step may perform a timing analysis of the design, and identify critical paths within the design that need to be improved by optimization. The characterization step may then assign timing constraints to those portions of the design, indicating the degree that they must be optimized to meet the desired timing goals. Because of the size of many designs, the characterization and optimization steps typically only operate on one module of the design at any given time. As such, the characterization step may assign timing constraints to the selected module, based upon the circuitry interfacing therewith. The module that the tools is currently operating on may be termed the local module, while all other modules may be termed remote modules.
After the characterization step is complete, the optimizer tool may perform an optimization step. The optimization step typically attempts to optimize the design such that all of the timing constraints assigned by the characterization step are satisfied. During the optimization step, the logic optimizer may, for example, remove logic from the design that is unnecessary, minimize the logic that is necessary to implement certain functions, increase the power of selected cells to improve performance, etc.
After the design has been optimized, the circuit designers typically verify that the resulting logic definition is correct and that the integrated circuit implements the expected function. This verification is currently achieved by timing and simulation software tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the behavior description as needed. These design iterations help to ensure that the design satisfies the desired requirements.
After timing verifications and functional simulation have been completed, placement and routing of the design's components is performed. These steps involve allocating components of the design to locations on the integrated circuit chip and interconnecting the components to form nets. Finally, final timing verification is performed after placement and routing is complete.
A problem in the above design process may occur when multi-cycle paths are incorporated into a design. Multi-cycle paths are data paths that have a propagation time that is longer than the clock period of an available clock signal. To accommodate the multi-cycle paths, a corresponding clock signal may be gated with a functional enable signal, thereby qualifying the clock signal. The functional enable signals may select which clock pulse of the corresponding clock signal is activated, and thus may functionally select at which clock cycle of the corresponding clock that new data is latched into a corresponding state device. This may allow the system to selectively make multi-cycle decisions.
Multi-cycle paths are particularly useful in high performance systems. In some systems, the clock periods are set to accommodate the worst case propagation time within the system. However, it has been found that to maximize performance, it may be desirable to set the raw clock period such that only the faster operations are accommodated, and the slower operations are allowed to be completed during a multi-cycle decision using a gated clocking scheme.
Typical logic optimizer tools cannot handle multi-cycle path designs, particularly when the source and destination state devices are located in separate modules within the design, and are optimized separately. As discussed more fully in co-pending U.S. patent application Ser. No. 08/752,616, filed Nov. 19, 1996, entitled "Method and Apparatus for Identifying Gated Clocks Within a Circuit Design Using a Standard Optimization Tool", typical logic optimizer tools may not properly identify gated clocks, and may thus incorrectly associate a particular clock signal with each state device, rather than the correct qualified clock signal. This may prohibit the proper optimization of a design that includes multi-cycle paths.
In addition to the above, and because logic optimizer tools typically only operate on a single module of a design at any given time, critical timing information may be lost. For example, for some logic optimizer tools, the only timing information passed from a remote module to a local module, via the characterization step discussed above, is the clock phase of the source latch and the worst case delay from the source latch to the boundary of local module. However, it may be necessary to further indicate which paths extending between the remote module and the local module are multi-cycle paths, and how many cycles are allowed for each path. Without this information, the multi-cycle paths may be improperly optimized and/or false errors may be reported by the logic optimizer tool.